Stability and Resolution Analysis of a Phase-Locked Loop Natural Frequency Tracking System for MEMS Fatigue Testing
نویسندگان
چکیده
An analysis of a nonlinear control system that was used to track the natural frequency of a MEMS resonator is presented in this paper. A phase-locked loop system is used to track the natural frequency of the resonator due to fatigue of the spring element. A model for the control system is established and the system behavior is analyzed using an averaging method. The analysis provides a quantitative criterion for selecting the control gain to achieve stability. Simulation results are shown to be in agreement with the theoretical analysis. Tracking accuracy under the presence of Brownian noise and capacitive position sensing noise is also analyzed by using a variance propagation equation for the nonlinear dynamic system utilizing a first-order Taylor series approximation. The theoretically estimated resolution is also found to be in good agreement with simulation results. @DOI: 10.1115/1.1514658#
منابع مشابه
High Speed Delay-Locked Loop for Multiple Clock Phase Generation
In this paper, a high speed delay-locked loop (DLL) architecture ispresented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which canbe triggered by double edges of the input signals. In addition, the blind zone is removed due to the elimination of reset signal. Theref...
متن کاملA-New-Closed-form-Mathematical-Approach-to-Achieve Minimum Phase Noise in Frequency Synthesizers
The aim of this paper is to minimize output phase noise for the pure signal synthesis in the frequency synthesizers. For this purpose, first, an exact mathematical model of phase locked loop (PLL) based frequency synthesizer is described and analyzed. Then, an exact closed-form formula in terms of synthesizer bandwidth and total output phase noise is extracted. Based on this formula, the phase ...
متن کاملDual Phase Detector Based Delay Locked Loop for High Speed Applications
In this paper a new architecture for delay locked loops will be presented. One of problems in phase-frequency detectors (PFD) is static phase offset or reset path delay. The proposed structure decreases the jitter resulted from PFD by switching two PFDs. In this new architecture, a conventional PFD is used before locking of DLL to decrease the amount of phase difference between input and outpu...
متن کاملDesign and Implementation of Digital Demodulator for Frequency Modulated CW Radar (RESEARCH NOTE)
Radar Signal Processing has been an interesting area of research for realization of programmable digital signal processor using VLSI design techniques. Digital Signal Processing (DSP) algorithms have been an integral design methodology for implementation of high speed application specific real-time systems especially for high resolution radar. CORDIC algorithm, in recent times, is turned out to...
متن کاملOn the Probability Density Function and Stability Properties for a Cross-Product Frequency-Locked Loop
The frequency locked-loop (FLL) has received new attention for modern Global Navigation Satellite Systems (GNSS) receivers, especially for its performance under severe noise interference and high dynamic environments. It has been shown that an FLL is more robust to interference and dynamics than a phase locked-loop (PLL). Therefore, it is beneficial to use an FLL as a fallback tracking loop whe...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2002